In recent years, applications in which LEDs or light-emitting diodes are used have become popular. Accompanying this trend, a number of LED driver ICs or integrated circuits have been used in to control the LEDs. An example of a convention LED driver is shown in FIG. 1, and a timing diagram corresponding to the general operation of the convention LED drive of FIG. 1 is shown in FIG. 2. Now, turning to FIG. 1, the reference numeral 100 generally designates the conventional LED driver. LED driver 100 is generally comprised of current source 102, amplifier 102, and transistors N1 through N4 (NMOS FETs) and P1 (PMOS FET).
In operation, transistors N1 and N2 operate as a current mirror circuit so that when reference current Iref flows through transistor N2, the mirror current also flows through transistor N1, forming output current Io. If transistor1 N2 and N1 have the same general structure and the size ratio (generally, 1:n), output current Io will be determined by the following equation: 1o=n*Iref. In principle, a constant current can be obtained; however, in practice, the output current Io will vary with changes in the output voltage due to the Early effect, which is undesirable.
One way of reducing this variation in the output current due to the Early effect is to employ the configuration of transistors N1 and N5, which are cascade-connected. Here, transistor N5 operates to suppress variations in the output current despite variations in the output voltage. To accomplish this, amplifier 104 is used to control the transistor N5, where the non-inverting input terminal of amplifier 104 is connected to the gate electrode of transistor N2 that sets reference current Iref and where the inverting input terminal of amplifier 104 is connected to the source terminal of output transistor N5 on the upper side of the cascade connection. Additionally, the output of amplifier 104 is connected to the gate terminal of transistor N5. Amplifier 104 operates to generally ensure that the voltage at the non-inverting input terminal and voltage at the inverting input terminal (the drain voltage of transistor N5) are generally the same. As a result, the gate and drain voltages of transistors N2 and N1, which form a current mirror circuit are the same, so that the circuit operation is unaffected by changes in the output voltage. Thus, amplifier 104 operates as a negative feedback circuit, and the gate potential of output transistor N5 is controlled corresponding to variations in the output voltage, so that the output current can be kept constant.
Now turning to FIG. 2, a timing diagram of the operation of the driver 100 is shown. At time t1, control signal transitions to from logic high to logic low. At time t1, the voltage at node s1 remains at logic high, while the voltage at node s2 transitions to logic high and the voltage at node s3 transitions to logic low. This results in the voltage at node s4 having to increase between times t1 and t2. Thus, the output current is not constant during the period from time t1 to t2. Therefore, there is a need for a circuit that provides a generally constant output current.